eProcessor: the first European open source processor is created in Spain


Europe is heavily dependent on technology designed and produced in the United States and China. That is why, in recent years, some things have been moving at the EU level so that this stops being the case, and have independence, especially in computing. Projects such as EPI, eProcessor, companies such as SiPearl, as well as the GAIA-X infrastructure have emerged from these movements.

Since most ISAs or architectures are proprietary and owned outside of Europe, open source It has been key for these projects to succeed. The ISA RISC-V it has brought hope, allowing these processors and accelerators to build on it without any restriction or limitation by geopolitical and geostrategic wars.

EPI (European Processor Initiative) is born

PPE logo

One of the first reactions of Europe, after the EDA (European Defense Agency) conference where the problems of technological and industrial dependence of the member countries were exposed, was to initiate a joint initiative called EPI (European Processor Initiative). Its objective is to bring together a consortium to implement the necessary mechanisms to have processors designed in Europe.

These chips, in principle, will not be for private use, but will focus on the HPC sector, that is, supercomputing. These high-performance machines are especially critical, and as a result of this project, EU data centers will be promoted to Exascale from 2023. They will also have application in other sectors such as the automotive and aerospace industries.

To make this possible, based on RISC-V for accelerators, while GPPs or general purpose processors will be based on IP ARM Cortex Neoverse cores, as they will allow them to speed up the design process and not start from scratch.

It has been leaked that the first SoC design would feature 72 ARM cores, 4-6 memory controllers with support for DDR5, HBM2E memory, and the RISC-V accelerator called EPAC. The processor would be manufactured in a 7nm node at TSMC.

EPI also has 26 partners from 10 different European countries, including Spain. One of the central pillars of the project is the Barcelona National Supercomputing Center (BCN). Spain is joined by partners such as Chalmers Tekniska Hoegskola AB from Sweden, Infineon Technologies from Germany, CEA from France, STMicroelectronics in Holland, the Università di Bologna in Italy, the Higher Technical Institute of Lisbon in Portugal, FORTH in Greece, or the ETH laboratory Zürich from Switzerland.

SiPearl, the private company, is created to provide the project with the ability to operate

SiPearl Logo

In order to operate, a private company has been created that will be in charge of managing the technologies resulting from this EPI project. His name is SiPearl and its headquarters are in France. In addition, they have opened a subsidiary in Germany and another in Spain, specifically in Barcelona, ​​in order to be close to their BSC partners.

This startup started with a public budget of 80 millones de euros, which are not enough to cover all the expenses that a project of such depth implies. Therefore, SiPearl will also be in charge of raising more than 100 million euros privately, mainly from shares.

Its co-founder and CEO, Philippe Notton, is doing a fantastic job recruiting some designers brought in from Silicon Valley, as well as the right staff with the experience to give the project all the guarantees. They are also looking for technological partners, such as Graphcore, a leading British company in terms of accelerating chips with artificial intelligence that are so important in HPC.

BSC a key partner: From the Lagarto chip to Drac

BSC Marenostrum

El BSC (Barcelona Supercomputing Center) it is a key piece of this project. Not only are they contributing to the design and development of these processors, but the Marenostrum 5 will already begin to test the fruits of this project ...


Lizard Chip eProcessor

The first Spanish microprocessor based on the RISC-V instruction set has been dubbed Lizard, and it is the first step to reach technological independence. However, behind this project there is a great effort and work coordinated by the BSC of the National Supercomputing Center of Spain, as well as the collaboration of the CSIC, and the UPC.

This design is very simple, and your objective is to carry out the first tests. It was manufactured using a node 65nm at TSMC, enough for the relative simplicity of this early prototype that it was tested in some benchmarks to see what it was capable of, and the results were quite positive. Even better than expected ...

In May 2019 the final design of this chip would be sent to the EUROPRACTICE platform of the EC, and after that about 100 copies of Lagarto would arrive in Barcelona to begin with the tests and to serve as a base for the accelerator for the HPC that is also being based on this ISA.


Drac eProcessor logo

The next step was DRAC (Designing RISC-V-bsed Accelerators for the next generation Computers). A chip designed for security applications, such as hardware encryption, as well as scientific applications such as genome analysis, simulation acceleration, or the autonomous vehicle sector.

Of course, DRAC is also led by the BSC and is based on the architecture of open source RISC-V. This project is expected to last about 3 years, in which up to 40 researchers will participate and will be coordinated by Miquel Moretó, a researcher from the Ramón y Cajal program at the UPC. In addition, the financing has been about 4 million euros, half coming from ERDF funds and the other half from the partners of this project.

This has already started to pay off. DVINO (DRAC Vector IN-Order) It is a chip derived from this project and of the first generation. As its name suggests, it is a well-ordered IC that includes a Lagarto core along with a Hydra vector processor designed for distributed computing.

La second generation improve chip performance by 15% and add new drivers and increase the area to 8.6 square millimeters.


RISC-V chip

eProcessor is the new step forward, a processor with versions planned for supercomputing and servers, as well as advanced driver assistance systems for vehicles (eg: ADAS), IoT, mobile devices, etc.

Again the BSC is the one involved in this project. It is the first open source European full-stack ecosystem and whose central pillar will be a CPU based on RISC-V and with a kernel with out-of-order execution. The Barcelona center will contribute its experience in the design of IP cores in HDL, emulation, and the necessary tools.

Along with the BSC, other important members at European level, such as Chalmers University of Technology, the Foundation for Research and Technology Hellas, Universita degli Studi di Roma La Sapienza, Cortus, Christmann Informationstechnik, Universität Bielefeld, Extoll GmbH, Thales and Exapsys, as well as the support of EuroHPC JU.

Hardware and software technologies will be developed and started testing on FPGAs to then give the salat to the ASICs. The first step will be to design a high-performance, high-efficiency RISC-V core. It will be a single-core and a dual-core with coherent off-chip link, although later they will start with more complex and powerful designs. The RISC-V-based vector accelerator will also be designed and traditional supercomputing workloads such as bioinformatics, AI, HPDA, etc. will be explored.

The eProcessor will also be very versatile and flexible at the time of scaling it, to be able to add more on-chip devices.

The next step: manufacturing

chip factory

The design of these chips will be European, what will not be is the manufacture. SiPearl is a fabless, and given the backwardness in terms of foundry manufacturing nodes in member countries, the design has been commissioned to TSMC, which will manufacture it in 7nm technology and using the novel 3D packaging technology called CoWoS (Chip-on-Wafer-on-Substrate).

However, the idea is not to depend on foreign factories for that, so the EU has also mobilized a large part of money to finance the updating of semiconductor manufacturing in the Old Continent. Specifically, it will allocate 145.000 million euros, with the aim of reaching a node with 2nm manufacturing technology in the short term.

This takes time, and is intended to reach 2-3 years seen. In addition, it seems that TSMC is collaborating to make this possible, and also the European ASML, which is the leader in the manufacture of advanced photolithography machines for the semiconductor industry, and which is based in the Netherlands ...

Nadia Calviño herself, Vice President of Economic Affairs and Digital Transformation has explained it like this: «Work is being done at the national and international level to see which Spanish and European companies can manufacture them«, In reference to these chips. Along the same lines was Thierry Breton's speech at the European Commission. And it is that the funds destined to the sector will come largely from the aid provided by the EU for the digital transformation and for the post-pandemic recovery.

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