Raspberry Pi has released two new specifications for PCIe FFC connectors, both for wiring and for the new standard for HAT+ or HAT Plus. This way, hardware or complements can be developed for the Raspberry Pi, specifically for versions 4 and 5, since it comes with specific specifications regarding mechanical dimensions and electrical compatibility.
Well, if you are interested in knowing these specifications for develop your own HAT or just out of curiosity, here you have all the details...
PCIe FFC connector wiring: specifications
The new Raspberry Pi 5 was announced a few months ago, and the Raspberry Pi Foundation is already moving some interesting things for this new SBC. For example, it has released the specifications of this new PCIe FFC connector which you can see in the previous image and in the PDF that I attach below.
Some people may have been experimenting with it and even released products like a M.2 HAT for the Raspberry Pi 5 since then, to be able to connect M.2 storage units, networks, etc., as we already mentioned before, even though the pinout and specifications were not available.
But now Raspberry Pi has officially released the specifications to make things easier with the PCIe FFC connector found on the Raspberry Pi 5, and probably future models as well. The 16-pin FFC connector with 0.5 mm pitch features a Single lane PCIe 2.0 interface (x1), something we already knew, but now the pin diagram and recommendations for the FFC cable (up to 50 mm in length with impedance controlled at 90R +/- 10%) have also been made available.
It is true that one PCIe Gen2 It may seem somewhat outdated, since on the PC we already have PCIe Gen 5, but the truth is that for this Raspberry Pi it is enough due to the speed it provides. For example, we can count on:
- Bandwidth: The transfer rate per lane is up to 5.0 GT/s (gigatransfers per second) per lane, that will be the maximum we can achieve with this standard. This gives a maximum theoretical speed of 500 MB/s in each direction.
- Lanes: As you may know, PCIe 2.0 supports configurations with different numbers of lanes, such as x1, x2, x4, x8, and x16. However, the Raspberry Pi, as I mentioned, only supports x1.
- Backward Compatibility: PCIe 2.0 is backward compatible with the previous version, PCIe 1.0. This means that PCIe 1.0 devices can work in PCIe 2.0 slots and vice versa, albeit at the transfer speed of the older version.
- Latency: Latency is typically lower compared to PCIe 1.0, which improves the performance of data transfers.
- Energy: PCIe 2.0 includes improved power management features, allowing for more efficient power consumption when the device is not in use.
It's important to note that these specifications are for PCIe 2.0 in general, and specific implementations may vary by chipset manufacturer and SBC. And, as Jeff Geerling demonstrated, PCIe Gen 3 can be enabled, although this is not official...
Download the PDF of the specifications
Raspberry Pi HAT+ standard: specifications
Having said that about the new PCIe FFC connector, now we move on to the HAT, and it has also officially released the standard Hardware on Top specifications for the hats that are launched for the new SBC Raspberry Pi 5, as introduced since 2014 to be able to expand the capabilities of this SBC, which has already become obsolete, and the new specification of the standard is now called HAT+ or HAT Plus.
Well, the specifications
- HAT+ must be electrically compatible with the STANDBY power state of the Raspberry Pi 5. Therefore, the 5V power path is on, but the 3.3V power path will be off. This is true on the Pi 4 and Pi 5, a state that is not present on the older SBC models. Additionally, note two details that may be important in this sense:
- WARM-STANDBY: in this case, the Raspberry Pi has all power paths enabled, the default mode in which the system is put when performing a "sudo halt" or a soft shutdown operation with the power button on the board. WARM-STANDBY is the default on Raspberry Pi OS, so both 5V and 3.3V are enabled, and that's why I measured a power consumption of 1.7W for the Raspberry Pi 5 when powered off. We can change /boot/config.txt (POWER_OFF_ON_HALT=1, WAKE_ON_GPIO=0) to reduce that to close to zero. So why is it not enabled by default? Because some HATs require both 5V and 3.3V, but HAT+ only needs the 5V one. Of course, it is also requested that access to other connectors and the Raspberry Pi 5 active cooler not be interfered with.
- STANDBY: in this case only the 5V line is powered, so the power management chip is powered. However, no other power supplies are enabled on the PMIC or the board. It can be configured to enter this mode using the "sudo halt" command or with the board's shutdown button using the EEPROM.
- Now the physical dimensions of the HAT do not matter as much as before. Therefore, specifications regarding dimensions are less prescriptive. That is, the HAT+ board only needs to connect to the 40-way GPIO header (including the ID_* pins), and have at least one mechanical mounting hole aligned with one of the four mounting holes of the Raspberry Pi, the rest is free for the designer.
- As for the content of the HAT's EEPROM memory, it has now been simplified to make things easier.
- A new specification or special class of HAT+ is now supported that can be stacked with an additional HAT+ on top, creating a stack of up to 2 HATs.
- On the other hand, the HAT+ boards will be electronically backward compatible with older models, so they can be used on Raspberry Pi SBC boards prior to the Pi 4 and 5. But only on an electronic level, as they may require updated firmware and software to work properly. Also add that one reason why the newly released HAT+ specification is still in draft phase is that the EEPROM utilities have yet to be updated for the new, simpler EEPROM parameters.
Download the PDF with specifications